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<div class="header">
  <div class="summary">
<a href="#nested-classes">Data Structures</a> &#124;
<a href="#define-members">Macros</a> &#124;
<a href="#func-members">Functions</a>  </div>
  <div class="headertitle"><div class="title">Generic Interrupt Controller Functions<div class="ingroups"><a class="el" href="group__CMSIS__Core__FunctionInterface.html">Core Peripherals</a></div></div></div>
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<p>The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC).  
<a href="#details">More...</a></p>
<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="nested-classes" name="nested-classes"></a>
Data Structures</h2></td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICInterface__Type.html">GICInterface_Type</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure type to access the Generic Interrupt Controller Interface (GICC)  <a href="structGICInterface__Type.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:"><td class="memItemLeft" align="right" valign="top">struct &#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a></td></tr>
<tr class="memdesc:"><td class="mdescLeft">&#160;</td><td class="mdescRight">Structure type to access the Generic Interrupt Controller Distributor (GICD)  <a href="structGICDistributor__Type.html#details">More...</a><br /></td></tr>
<tr class="separator:"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="define-members" name="define-members"></a>
Macros</h2></td></tr>
<tr class="memitem:ga82e193c0016a9377274756b2673464a6"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">GICDistributor</a>&#160;&#160;&#160;((<a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a>      *)     GIC_DISTRIBUTOR_BASE )</td></tr>
<tr class="memdesc:ga82e193c0016a9377274756b2673464a6"><td class="mdescLeft">&#160;</td><td class="mdescRight">GIC Distributor register set access pointer.  <br /></td></tr>
<tr class="separator:ga82e193c0016a9377274756b2673464a6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga31a083dbdc5cb84178dbf184286180e3"><td class="memItemLeft" align="right" valign="top">#define&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a>&#160;&#160;&#160;((<a class="el" href="structGICInterface__Type.html">GICInterface_Type</a>        *)     GIC_INTERFACE_BASE )</td></tr>
<tr class="memdesc:ga31a083dbdc5cb84178dbf184286180e3"><td class="mdescLeft">&#160;</td><td class="mdescRight">GIC Interface register set access pointer.  <br /></td></tr>
<tr class="separator:ga31a083dbdc5cb84178dbf184286180e3"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a id="func-members" name="func-members"></a>
Functions</h2></td></tr>
<tr class="memitem:ga0f44df6823e90178183257e096e5cac6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6">GIC_EnableDistributor</a> (void)</td></tr>
<tr class="memdesc:ga0f44df6823e90178183257e096e5cac6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the interrupt distributor using the GIC's CTLR register.  <br /></td></tr>
<tr class="separator:ga0f44df6823e90178183257e096e5cac6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga363311538d4a4d750197b9936505d466"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga363311538d4a4d750197b9936505d466">GIC_DisableDistributor</a> (void)</td></tr>
<tr class="memdesc:ga363311538d4a4d750197b9936505d466"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the interrupt distributor using the GIC's CTLR register.  <br /></td></tr>
<tr class="separator:ga363311538d4a4d750197b9936505d466"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga7d93d39736ef5e379e6511430ee6e75f"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga7d93d39736ef5e379e6511430ee6e75f">GIC_DistributorInfo</a> (void)</td></tr>
<tr class="memdesc:ga7d93d39736ef5e379e6511430ee6e75f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the GIC's TYPER register.  <br /></td></tr>
<tr class="separator:ga7d93d39736ef5e379e6511430ee6e75f"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga1481d0cdf78f8c93fb2a710a519c4dc6">GIC_DistributorImplementer</a> (void)</td></tr>
<tr class="memdesc:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Reads the GIC's IIDR register.  <br /></td></tr>
<tr class="separator:ga1481d0cdf78f8c93fb2a710a519c4dc6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b">GIC_SetTarget</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t cpu_target)</td></tr>
<tr class="memdesc:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the GIC's ITARGETSR register for the given interrupt.  <br /></td></tr>
<tr class="separator:gae86bba705d0d4ef812b84d29d7b3ca2b"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafccf881f9517592f30489bcabcb738a8"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gafccf881f9517592f30489bcabcb738a8">GIC_GetTarget</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gafccf881f9517592f30489bcabcb738a8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the GIC's ITARGETSR register.  <br /></td></tr>
<tr class="separator:gafccf881f9517592f30489bcabcb738a8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga758e5600d7f891e4f2f551bb45d07fce"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga758e5600d7f891e4f2f551bb45d07fce">GIC_EnableInterface</a> (void)</td></tr>
<tr class="memdesc:ga758e5600d7f891e4f2f551bb45d07fce"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enable the CPU's interrupt interface.  <br /></td></tr>
<tr class="separator:ga758e5600d7f891e4f2f551bb45d07fce"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga0605877ad627c1f4320e518725fd103e"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga0605877ad627c1f4320e518725fd103e">GIC_DisableInterface</a> (void)</td></tr>
<tr class="memdesc:ga0605877ad627c1f4320e518725fd103e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disable the CPU's interrupt interface.  <br /></td></tr>
<tr class="separator:ga0605877ad627c1f4320e518725fd103e"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gafc08bbc58b25fef0d24003313fd16eb8"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE <a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a> (void)</td></tr>
<tr class="memdesc:gafc08bbc58b25fef0d24003313fd16eb8"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the CPU's IAR register.  <br /></td></tr>
<tr class="separator:gafc08bbc58b25fef0d24003313fd16eb8"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gac23f090f572a058b4a737f6613ded9cd"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd">GIC_EndInterrupt</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gac23f090f572a058b4a737f6613ded9cd"><td class="mdescLeft">&#160;</td><td class="mdescRight">Writes the given interrupt number to the CPU's EOIR register.  <br /></td></tr>
<tr class="separator:gac23f090f572a058b4a737f6613ded9cd"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaeba215d9c4ec3599e0a168800288c3f3"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaeba215d9c4ec3599e0a168800288c3f3">GIC_EnableIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gaeba215d9c4ec3599e0a168800288c3f3"><td class="mdescLeft">&#160;</td><td class="mdescRight">Enables the given interrupt using GIC's ISENABLER register.  <br /></td></tr>
<tr class="separator:gaeba215d9c4ec3599e0a168800288c3f3"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2102399d255690c0674209a6faeec13d"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d">GIC_DisableIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga2102399d255690c0674209a6faeec13d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Disables the given interrupt using GIC's ICENABLER register.  <br /></td></tr>
<tr class="separator:ga2102399d255690c0674209a6faeec13d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga18fbddf7f3594df141c97f61a71da47c"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga18fbddf7f3594df141c97f61a71da47c">GIC_SetPendingIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga18fbddf7f3594df141c97f61a71da47c"><td class="mdescLeft">&#160;</td><td class="mdescRight">Sets the given interrupt as pending using GIC's ISPENDR register.  <br /></td></tr>
<tr class="separator:ga18fbddf7f3594df141c97f61a71da47c"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga5ad17ad70f23d1ff36015ffac33d383d">GIC_ClearPendingIRQ</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="mdescLeft">&#160;</td><td class="mdescRight">Clears the given interrupt from being pending using GIC's ICPENDR register.  <br /></td></tr>
<tr class="separator:ga5ad17ad70f23d1ff36015ffac33d383d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga27b9862b58290276851ec669cabf0f71"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t priority)</td></tr>
<tr class="memdesc:ga27b9862b58290276851ec669cabf0f71"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the priority for the given interrupt in the GIC's IPRIORITYR register.  <br /></td></tr>
<tr class="separator:ga27b9862b58290276851ec669cabf0f71"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga397048004654f792649742f95bf8ae67"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:ga397048004654f792649742f95bf8ae67"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the current interrupt priority from GIC's IPRIORITYR register.  <br /></td></tr>
<tr class="separator:ga397048004654f792649742f95bf8ae67"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">GIC_SetInterfacePriorityMask</a> (uint32_t priority)</td></tr>
<tr class="memdesc:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="mdescLeft">&#160;</td><td class="mdescRight">Set the interrupt priority mask using CPU's PMR register.  <br /></td></tr>
<tr class="separator:gaa5eb0e76dbc89596e1ce47ddb9edc4a0"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga2c5f9e5637560fc9d5c29d772580a728"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2c5f9e5637560fc9d5c29d772580a728">GIC_GetInterfacePriorityMask</a> (void)</td></tr>
<tr class="memdesc:ga2c5f9e5637560fc9d5c29d772580a728"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the current interrupt priority mask from CPU's PMR register.  <br /></td></tr>
<tr class="separator:ga2c5f9e5637560fc9d5c29d772580a728"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6">GIC_SetBinaryPoint</a> (uint32_t binary_point)</td></tr>
<tr class="memdesc:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="mdescLeft">&#160;</td><td class="mdescRight">Configures the group priority and subpriority split point using CPU's BPR register.  <br /></td></tr>
<tr class="separator:ga5dfedeb5403656a77e0fef4e1cc2c0c6"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaa7046d8206ddd4696716726e68f85906"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaa7046d8206ddd4696716726e68f85906">GIC_GetBinaryPoint</a> (void)</td></tr>
<tr class="memdesc:gaa7046d8206ddd4696716726e68f85906"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read the current group priority and subpriority split point from CPU's BPR register.  <br /></td></tr>
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<tr class="memitem:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gabc88483ecf94a2c222b644ecfa60eb9f">GIC_GetIRQStatus</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn)</td></tr>
<tr class="memdesc:gabc88483ecf94a2c222b644ecfa60eb9f"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the status for a given interrupt.  <br /></td></tr>
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<tr class="memitem:ga2de8850780af26e802ee4cc43e9da6e9"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga2de8850780af26e802ee4cc43e9da6e9">GIC_SendSGI</a> (<a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> IRQn, uint32_t target_list, uint32_t filter_list)</td></tr>
<tr class="memdesc:ga2de8850780af26e802ee4cc43e9da6e9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Generate a software interrupt using GIC's SGIR register.  <br /></td></tr>
<tr class="separator:ga2de8850780af26e802ee4cc43e9da6e9"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga8bb27e1bab132a8df44190adb996c2a1"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga8bb27e1bab132a8df44190adb996c2a1">GIC_GetHighPendingIRQ</a> (void)</td></tr>
<tr class="memdesc:ga8bb27e1bab132a8df44190adb996c2a1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Get the interrupt number of the highest interrupt pending from CPU's HPPIR register.  <br /></td></tr>
<tr class="separator:ga8bb27e1bab132a8df44190adb996c2a1"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE uint32_t&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#gaba1b2665cdda47fc0bc3d7b90690dc50">GIC_GetInterfaceId</a> (void)</td></tr>
<tr class="memdesc:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="mdescLeft">&#160;</td><td class="mdescRight">Provides information about the implementer and revision of the CPU interface.  <br /></td></tr>
<tr class="separator:gaba1b2665cdda47fc0bc3d7b90690dc50"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga07acd03d02683bb6e33e7f57f5f371d1">GIC_DistInit</a> (void)</td></tr>
<tr class="memdesc:ga07acd03d02683bb6e33e7f57f5f371d1"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the interrupt distributor.  <br /></td></tr>
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<tr class="memitem:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga1c93f8af9f428cda8ec066bf4bfbade9">GIC_CPUInterfaceInit</a> (void)</td></tr>
<tr class="memdesc:ga1c93f8af9f428cda8ec066bf4bfbade9"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize the CPU's interrupt interface.  <br /></td></tr>
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<tr class="memitem:ga818881f69aae3eef6eb996bee6f6c63e"><td class="memItemLeft" align="right" valign="top">__STATIC_INLINE void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="group__GIC__functions.html#ga818881f69aae3eef6eb996bee6f6c63e">GIC_Enable</a> (void)</td></tr>
<tr class="memdesc:ga818881f69aae3eef6eb996bee6f6c63e"><td class="mdescLeft">&#160;</td><td class="mdescRight">Initialize and enable the GIC.  <br /></td></tr>
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</table>
<a name="details" id="details"></a><h2 class="groupheader">Description</h2>
<p>The Generic Interrupt Controller Functions grant access to the configuration, control and status registers of the Generic Interrupt Controller (GIC). </p>
<p>Reference: <a href="http://infocenter.arm.com/help/topic/com.arm.doc.ihi0069c/index.html">Generic Interrupt Controller Architecture Specificaton</a>.</p>
<p>The following table shows the register naming of CMSIS in correlation with various technical reference manuals.</p>
<table class="markdownTable">
<tr class="markdownTableHead">
<th class="markdownTableHeadLeft">CMSIS Register Name   </th><th class="markdownTableHeadLeft">Cortex-A5 TRM   </th><th class="markdownTableHeadLeft">Cortex-A7 TRM   </th><th class="markdownTableHeadLeft">Cortex-A9 TRM    </th></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><b>GIC Distributor</b>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a6ca67d9838ab3425864207c3a0399bd7">GICDistributor-&gt;CTLR</a>   </td><td class="markdownTableBodyLeft">ICDDCR   </td><td class="markdownTableBodyLeft">GICD_CTLR   </td><td class="markdownTableBodyLeft">ICDDCR    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207">GICDistributor-&gt;TYPER</a>   </td><td class="markdownTableBodyLeft">ICDICTR   </td><td class="markdownTableBodyLeft">GICD_TYPER   </td><td class="markdownTableBodyLeft">ICDICTR    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722">GICDistributor-&gt;IIDR</a>   </td><td class="markdownTableBodyLeft">ICDIIDR   </td><td class="markdownTableBodyLeft">GICD_IIDR   </td><td class="markdownTableBodyLeft">ICDIIDR    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#ae24f260e27065660a2059803293084f2">GICDistributor-&gt;STATUSR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#afbdd372578e2cd6f998320282cc8ed25">GICDistributor-&gt;SETSPI_NSR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a2f584d3fbeaa355faf234f2ee57d1168">GICDistributor-&gt;CLRSPI_NSR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a6a9effdd633c6e75651d9f53caace306">GICDistributor-&gt;IGROUPR[]</a>   </td><td class="markdownTableBodyLeft">ICDISR   </td><td class="markdownTableBodyLeft">GICD_IGROUPRn   </td><td class="markdownTableBodyLeft">ICDISRn    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a1da3a2066b64644a0bb8a3066075ba87">GICDistributor-&gt;ISENABLER[]</a>   </td><td class="markdownTableBodyLeft">ICDISER   </td><td class="markdownTableBodyLeft">GICD_ISENABLERn   </td><td class="markdownTableBodyLeft">ICDISERn    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a390fa9f2f460951b2c6094932d890807">GICDistributor-&gt;ICENABLER[]</a>   </td><td class="markdownTableBodyLeft">ICDICER   </td><td class="markdownTableBodyLeft">GICD_ICENABLERn   </td><td class="markdownTableBodyLeft">ICDICERn    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5">GICDistributor-&gt;ISPENDR[]</a>   </td><td class="markdownTableBodyLeft">ICDISPR   </td><td class="markdownTableBodyLeft">GICD_ISPENDRn   </td><td class="markdownTableBodyLeft">ICDISPRn    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a0155cb4637845258e4ee76cd93cca2a6">GICDistributor-&gt;ICPENDR[]</a>   </td><td class="markdownTableBodyLeft">ICDICPR   </td><td class="markdownTableBodyLeft">GICD_ICPENDRn   </td><td class="markdownTableBodyLeft">ICDICPRn    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4">GICDistributor-&gt;ISACTIVER[]</a>   </td><td class="markdownTableBodyLeft">ICDABR   </td><td class="markdownTableBodyLeft">GICD_ISACTIVERn   </td><td class="markdownTableBodyLeft">ICDABRn    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#ac0fd4c1ad19b5a332e403bb9966ba967">GICDistributor-&gt;ICACTIVER[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICD_ICACTIVERn   </td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a08fa902293567e85dc6398dab58afaa9">GICDistributor-&gt;IPRIORITYR[]</a>   </td><td class="markdownTableBodyLeft">ICDIPR   </td><td class="markdownTableBodyLeft">GICD_IPRIORITYRn   </td><td class="markdownTableBodyLeft">ICDIPRn    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">GICDistributor-&gt;ITARGETSR[]</a>   </td><td class="markdownTableBodyLeft">ICDIPTR   </td><td class="markdownTableBodyLeft">GICD_ITARGETSRn   </td><td class="markdownTableBodyLeft">ICDIPTRn    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a9b306a630388c795d3cd32fc2e23a2b5">GICDistributor-&gt;ICFGR[]</a>   </td><td class="markdownTableBodyLeft">ICDICFR   </td><td class="markdownTableBodyLeft">GICD_ICFGRn   </td><td class="markdownTableBodyLeft">ICDICFRn    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689">GICDistributor-&gt;IGRPMODR[0]</a>   </td><td class="markdownTableBodyLeft">ICDPPIS   </td><td class="markdownTableBodyLeft">GICD_PPISR   </td><td class="markdownTableBodyLeft">ppi_status    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#ae9eeb19ca95d0b95828f1f98700b5689">GICDistributor-&gt;IGRPMODR[31:1]</a>   </td><td class="markdownTableBodyLeft">ICDSPIS   </td><td class="markdownTableBodyLeft">GICD_SPISRn   </td><td class="markdownTableBodyLeft">spi_status    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a644abefb7064e434db20cc6dab5fe5f1">GICDistributor-&gt;NSACR[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a6ac65c4a5394926cc9518753a00d4da1">GICDistributor-&gt;SGIR</a>   </td><td class="markdownTableBodyLeft">ICDSGIR   </td><td class="markdownTableBodyLeft">GICD_SGIR   </td><td class="markdownTableBodyLeft">ICDSGIR    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a644a70cf4c12093c0277ce01f194b69b">GICDistributor-&gt;CPENDSGIR[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICD_CPENDSGIRn   </td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#ae40b4a50d9766c2bbf57441f68094f41">GICDistributor-&gt;SPENDSGIR[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICD_SPENDSGIRn   </td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICDistributor__Type.html#a73e0c679e5f45710deea474ab0d39cdb">GICDistributor-&gt;IROUTER[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><b>GIC Interface</b>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">GICInterface-&gt;CTLR</a>   </td><td class="markdownTableBodyLeft">ICPICR   </td><td class="markdownTableBodyLeft">GICC_CTLR   </td><td class="markdownTableBodyLeft">ICCICR    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a0edadabc6e3ce1f36d820f0b52bc143b">GICInterface-&gt;PMR</a>   </td><td class="markdownTableBodyLeft">ICCIPMR   </td><td class="markdownTableBodyLeft">GICC_PMRn   </td><td class="markdownTableBodyLeft">ICCPMR    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829">GICInterface-&gt;BPR</a>   </td><td class="markdownTableBodyLeft">ICCBPR   </td><td class="markdownTableBodyLeft">GICC_BPR   </td><td class="markdownTableBodyLeft">ICCBPR    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea">GICInterface-&gt;IAR</a>   </td><td class="markdownTableBodyLeft">ICCIAR   </td><td class="markdownTableBodyLeft">GICC_IAR   </td><td class="markdownTableBodyLeft">ICCIAR    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a4b9baa43aae026438bad64e63df17cdb">GICInterface-&gt;EOIR</a>   </td><td class="markdownTableBodyLeft">ICCEOIR   </td><td class="markdownTableBodyLeft">GICC_EOIR   </td><td class="markdownTableBodyLeft">ICCEOIR    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a37762d42768ecb3d1302f34abc7f2821">GICInterface-&gt;RPR</a>   </td><td class="markdownTableBodyLeft">ICCRPR   </td><td class="markdownTableBodyLeft">GICC_RPR   </td><td class="markdownTableBodyLeft">ICCRPR    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6">GICInterface-&gt;HPPIR</a>   </td><td class="markdownTableBodyLeft">ICCHPIR   </td><td class="markdownTableBodyLeft">GICC_HPPIR   </td><td class="markdownTableBodyLeft">ICCHPIR    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a6d3ca9eaae5e0ac38f20846a1e67180d">GICInterface-&gt;ABPR</a>   </td><td class="markdownTableBodyLeft">ICCABPR   </td><td class="markdownTableBodyLeft">GICC_ABPR   </td><td class="markdownTableBodyLeft">ICCABPR    </td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a849e9ead6e9ced78dc6f0ba9256dd5a6">GICInterface-&gt;AIAR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_AIAR   </td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a89d5a920c2b91b4b7bd0312ba4c38a89">GICInterface-&gt;AEOIR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_AEOIR   </td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a12f25dec95ab3dd13a477573fab4b9c8">GICInterface-&gt;AHPPIR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_AHPPIR   </td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#abd978b408fb69b7887be2c422f48ce7e">GICInterface-&gt;STATUSR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#aebae4bdcd3930372d639b85c5c9301e8">GICInterface-&gt;APR[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_APR0   </td><td class="markdownTableBodyLeft"></td></tr>
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<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#ade3473ace2a8bf7c79a0251457be20f4">GICInterface-&gt;NSAPR[]</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_NSAPR0   </td><td class="markdownTableBodyLeft"></td></tr>
<tr class="markdownTableRowEven">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf">GICInterface-&gt;IIDR</a>   </td><td class="markdownTableBodyLeft">ICCIIDR   </td><td class="markdownTableBodyLeft">GICC_IIDR   </td><td class="markdownTableBodyLeft">ICCIDR    </td></tr>
<tr class="markdownTableRowOdd">
<td class="markdownTableBodyLeft"><a class="el" href="structGICInterface__Type.html#a554bd1f88421df3189c664b9fd9c02aa">GICInterface-&gt;DIR</a>   </td><td class="markdownTableBodyLeft"></td><td class="markdownTableBodyLeft">GICC_DIR   </td><td class="markdownTableBodyLeft"></td></tr>
</table>
<h2 class="groupheader">Macro Definition Documentation</h2>
<a id="ga82e193c0016a9377274756b2673464a6" name="ga82e193c0016a9377274756b2673464a6"></a>
<h2 class="memtitle"><span class="permalink"><a href="#ga82e193c0016a9377274756b2673464a6">&#9670;&#160;</a></span>GICDistributor</h2>

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          <td class="memname">#define GICDistributor&#160;&#160;&#160;((<a class="el" href="structGICDistributor__Type.html">GICDistributor_Type</a>      *)     GIC_DISTRIBUTOR_BASE )</td>
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<p>GIC Distributor register set access pointer. </p>
<p>Use GICDistributor to access the GIC Distributor registers.</p>
<p><b>Example:</b> </p><div class="fragment"><div class="line"><a class="code hl_define" href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">GICDistributor</a>-&gt;CTRL |= 1; <span class="comment">// Enable group 0 interrupts</span></div>
<div class="ttc" id="agroup__GIC__functions_html_ga82e193c0016a9377274756b2673464a6"><div class="ttname"><a href="group__GIC__functions.html#ga82e193c0016a9377274756b2673464a6">GICDistributor</a></div><div class="ttdeci">#define GICDistributor</div><div class="ttdoc">GIC Distributor register set access pointer.</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#ga31a083dbdc5cb84178dbf184286180e3">&#9670;&#160;</a></span>GICInterface</h2>

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          <td class="memname">#define GICInterface&#160;&#160;&#160;((<a class="el" href="structGICInterface__Type.html">GICInterface_Type</a>        *)     GIC_INTERFACE_BASE )</td>
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<p>GIC Interface register set access pointer. </p>
<p>Use GICInterface to access the GIC Interface registers.</p>
<p><b>Example:</b> </p><div class="fragment"><div class="line"><a class="code hl_define" href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a>-&gt;CTLR |= 1; <span class="comment">// Enable interrupt signaling</span></div>
<div class="ttc" id="agroup__GIC__functions_html_ga31a083dbdc5cb84178dbf184286180e3"><div class="ttname"><a href="group__GIC__functions.html#ga31a083dbdc5cb84178dbf184286180e3">GICInterface</a></div><div class="ttdeci">#define GICInterface</div><div class="ttdoc">GIC Interface register set access pointer.</div></div>
</div><!-- fragment --> 
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<h2 class="groupheader">Function Documentation</h2>
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<h2 class="memtitle"><span class="permalink"><a href="#gafc08bbc58b25fef0d24003313fd16eb8">&#9670;&#160;</a></span>GIC_AcknowledgePending()</h2>

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          <td class="memname">__STATIC_INLINE <a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a> GIC_AcknowledgePending </td>
          <td>(</td>
          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
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<p>Read the CPU's IAR register. </p>
<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#aa48569605fc0c163e1db35321b4c76ea" title="Offset: 0x00C (R/ ) Interrupt Acknowledge Register.">GICInterface_Type::IAR</a></dd></dl>
<p>Provides the interrupt number of the highest priority interrupt pending. A read of this register acts as an acknowledge for the interrupt.</p>
<p>The read returns a spurious interrupt number of 1023 if any of the following apply:</p><ul>
<li>Forwarding of interrupts by the Distributor to the CPU interface is disabled.</li>
<li>Signaling of interrupts by the CPU interface to the connected PE is disabled.</li>
<li>There are no pending interrupts on the CPU interface with sufficient priority for the interface to signal it to the PE.</li>
</ul>
<dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#gac23f090f572a058b4a737f6613ded9cd" title="Writes the given interrupt number to the CPU&#39;s EOIR register.">GIC_EndInterrupt</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5ad17ad70f23d1ff36015ffac33d383d">&#9670;&#160;</a></span>GIC_ClearPendingIRQ()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_ClearPendingIRQ </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
          <td></td>
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<p>Clears the given interrupt from being pending using GIC's ICPENDR register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be enabled.</td></tr>
  </table>
  </dd>
</dl>
<p>Removes the pending state from the corresponding interrupt. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga1c93f8af9f428cda8ec066bf4bfbade9">&#9670;&#160;</a></span>GIC_CPUInterfaceInit()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_CPUInterfaceInit </td>
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          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
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<p>Initialize the CPU's interrupt interface. </p>
<p>All software generated (SGIs) and private peripheral interrupts (PPIs) are initialized to be</p><ul>
<li>disabled</li>
<li>level-sensitive, 1-N model</li>
<li>priority 0x7F and the interrupt interface is enabled.</li>
</ul>
<p>The binary point is set to zero.</p>
<p>The interrupt priority mask is set to 0xFF.</p>
<dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d" title="Disables the given interrupt using GIC&#39;s ICENABLER register.">GIC_DisableIRQ</a><br  />
GIC_SetLevelModel<br  />
<a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71" title="Set the priority for the given interrupt in the GIC&#39;s IPRIORITYR register.">GIC_SetPriority</a><br  />
<a class="el" href="group__GIC__functions.html#ga758e5600d7f891e4f2f551bb45d07fce" title="Enable the CPU&#39;s interrupt interface.">GIC_EnableInterface</a><br  />
<a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6" title="Configures the group priority and subpriority split point using CPU&#39;s BPR register.">GIC_SetBinaryPoint</a><br  />
<a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0" title="Set the interrupt priority mask using CPU&#39;s PMR register.">GIC_SetInterfacePriorityMask</a><br  />
</dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga363311538d4a4d750197b9936505d466">&#9670;&#160;</a></span>GIC_DisableDistributor()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_DisableDistributor </td>
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          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
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<p>Disable the interrupt distributor using the GIC's CTLR register. </p>
<p>Globally disable the forwarding of interrupts to the CPU interfaces. </p><dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6" title="Enable the interrupt distributor using the GIC&#39;s CTLR register.">GIC_EnableDistributor</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0605877ad627c1f4320e518725fd103e">&#9670;&#160;</a></span>GIC_DisableInterface()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_DisableInterface </td>
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<p>Disable the CPU's interrupt interface. </p>
<p>Resets the Enable bit in the local CPUs <a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">CTLR</a> register. Only the CPU executing the call is affected. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2102399d255690c0674209a6faeec13d">&#9670;&#160;</a></span>GIC_DisableIRQ()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_DisableIRQ </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Disables the given interrupt using GIC's ICENABLER register. </p>
<dl class="params"><dt>Parameters</dt><dd>
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    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be disabled.</td></tr>
  </table>
  </dd>
</dl>
<p>Disables forwarding of the corresponding interrupt to the CPU interfaces. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga07acd03d02683bb6e33e7f57f5f371d1">&#9670;&#160;</a></span>GIC_DistInit()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_DistInit </td>
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<p>Initialize the interrupt distributor. </p>
<p>All shared peripheral interrupts (SPIs) are initialized to be</p><ul>
<li>disabled</li>
<li>level-sensitive, 1-N model</li>
<li>priority 0x7F</li>
<li>targeting CPU0 and the distributor is enabled.</li>
</ul>
<dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga2102399d255690c0674209a6faeec13d" title="Disables the given interrupt using GIC&#39;s ICENABLER register.">GIC_DisableIRQ</a><br  />
GIC_SetLevelModel<br  />
<a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71" title="Set the priority for the given interrupt in the GIC&#39;s IPRIORITYR register.">GIC_SetPriority</a><br  />
<a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b" title="Sets the GIC&#39;s ITARGETSR register for the given interrupt.">GIC_SetTarget</a><br  />
<a class="el" href="group__GIC__functions.html#ga0f44df6823e90178183257e096e5cac6" title="Enable the interrupt distributor using the GIC&#39;s CTLR register.">GIC_EnableDistributor</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga1481d0cdf78f8c93fb2a710a519c4dc6">&#9670;&#160;</a></span>GIC_DistributorImplementer()</h2>

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          <td class="memname">__STATIC_INLINE uint32_t GIC_DistributorImplementer </td>
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          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
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<p>Reads the GIC's IIDR register. </p>
<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICDistributor__Type.html#acebf65dae4cb82cd3c7deeefca9c9722" title="Offset: 0x008 (R/ ) Distributor Implementer Identification Register.">GICDistributor_Type::IIDR</a></dd></dl>
<p>Provides information about the implementer and revision of the Distributor. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga7d93d39736ef5e379e6511430ee6e75f">&#9670;&#160;</a></span>GIC_DistributorInfo()</h2>

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          <td class="memname">__STATIC_INLINE uint32_t GIC_DistributorInfo </td>
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          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
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<p>Read the GIC's TYPER register. </p>
<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICDistributor__Type.html#a405823d97dc90dd9d397a3980e2cd207" title="Offset: 0x004 (R/ ) Interrupt Controller Type Register.">GICDistributor_Type::TYPER</a></dd></dl>
<p>Provides information about the configuration of the GIC. It indicates:</p><ul>
<li>whether the GIC implements the Security Extensions</li>
<li>the maximum number of interrupt IDs that the GIC supports</li>
<li>the number of CPU interfaces implemented</li>
<li>if the GIC implements the Security Extensions, the maximum number of implemented Lockable Shared Peripheral Interrupts (LSPIs). </li>
</ul>

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<h2 class="memtitle"><span class="permalink"><a href="#ga818881f69aae3eef6eb996bee6f6c63e">&#9670;&#160;</a></span>GIC_Enable()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_Enable </td>
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          <td class="paramname"></td><td>)</td>
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<p>Initialize and enable the GIC. </p>
<p>Initializes the distributor and the cpu interface.</p>
<dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga07acd03d02683bb6e33e7f57f5f371d1" title="Initialize the interrupt distributor.">GIC_DistInit</a> <a class="el" href="group__GIC__functions.html#ga1c93f8af9f428cda8ec066bf4bfbade9" title="Initialize the CPU&#39;s interrupt interface.">GIC_CPUInterfaceInit</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga0f44df6823e90178183257e096e5cac6">&#9670;&#160;</a></span>GIC_EnableDistributor()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_EnableDistributor </td>
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<p>Enable the interrupt distributor using the GIC's CTLR register. </p>
<p>Globally enable the forwarding of interrupts to the CPU interfaces. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga758e5600d7f891e4f2f551bb45d07fce">&#9670;&#160;</a></span>GIC_EnableInterface()</h2>

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          <td class="paramtype">void&#160;</td>
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<p>Enable the CPU's interrupt interface. </p>
<p>Sets the Enable bit in the local CPUs <a class="el" href="structGICInterface__Type.html#a5969edab40aa24e4d96e072af187a3a9">CTLR</a> register. Only the CPU executing the call is affected. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaeba215d9c4ec3599e0a168800288c3f3">&#9670;&#160;</a></span>GIC_EnableIRQ()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_EnableIRQ </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Enables the given interrupt using GIC's ISENABLER register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be enabled.</td></tr>
  </table>
  </dd>
</dl>
<p>Enables forwarding of the corresponding interrupt to the CPU interfaces. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gac23f090f572a058b4a737f6613ded9cd">&#9670;&#160;</a></span>GIC_EndInterrupt()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_EndInterrupt </td>
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          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Writes the given interrupt number to the CPU's EOIR register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be signaled as finished.</td></tr>
  </table>
  </dd>
</dl>
<p>A write to this register performs priority drop for the specified interrupt.</p>
<p>For nested interrupts, the order of calls to this function must be the reverse of the order of interrupt acknowledgement, i.e. calls to <a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a>. Behavior is UNPREDICTABLE if:</p><ul>
<li>This ordering constraint is not maintained.</li>
<li>The given interrupt number does not match an active interrupt, or the ID of a spurious interrupt.</li>
<li>The given interrupt number does not match the last valid interrupt value returned by <a class="el" href="group__GIC__functions.html#gafc08bbc58b25fef0d24003313fd16eb8">GIC_AcknowledgePending</a>. </li>
</ul>

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<h2 class="memtitle"><span class="permalink"><a href="#gaa7046d8206ddd4696716726e68f85906">&#9670;&#160;</a></span>GIC_GetBinaryPoint()</h2>

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<p>Read the current group priority and subpriority split point from CPU's BPR register. </p>
<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#a949317484547dc1db89c9f7ab40d1829" title="Offset: 0x008 (R/W) Binary Point Register.">GICInterface_Type::BPR</a></dd></dl>
<dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga5dfedeb5403656a77e0fef4e1cc2c0c6" title="Configures the group priority and subpriority split point using CPU&#39;s BPR register.">GIC_SetBinaryPoint</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga8bb27e1bab132a8df44190adb996c2a1">&#9670;&#160;</a></span>GIC_GetHighPendingIRQ()</h2>

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          <td class="paramname"></td><td>)</td>
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<p>Get the interrupt number of the highest interrupt pending from CPU's HPPIR register. </p>
<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#af793cd280a74bf73cca8c4fedfc329d6" title="Offset: 0x018 (R/ ) Highest Priority Pending Interrupt Register.">GICInterface_Type::HPPIR</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gaba1b2665cdda47fc0bc3d7b90690dc50">&#9670;&#160;</a></span>GIC_GetInterfaceId()</h2>

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          <td class="memname">__STATIC_INLINE uint32_t GIC_GetInterfaceId </td>
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          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
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<p>Provides information about the implementer and revision of the CPU interface. </p>
<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#aee78d0b6f64a7b47fbd730aabfcc86cf" title="Offset: 0x0FC (R/ ) CPU Interface Identification Register.">GICInterface_Type::IIDR</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2c5f9e5637560fc9d5c29d772580a728">&#9670;&#160;</a></span>GIC_GetInterfacePriorityMask()</h2>

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          <td class="memname">__STATIC_INLINE uint32_t GIC_GetInterfacePriorityMask </td>
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          <td class="paramtype">void&#160;</td>
          <td class="paramname"></td><td>)</td>
          <td></td>
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<p>Read the current interrupt priority mask from CPU's PMR register. </p>
<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICInterface__Type.html#a0edadabc6e3ce1f36d820f0b52bc143b" title="Offset: 0x004 (R/W) Interrupt Priority Mask Register.">GICInterface_Type::PMR</a></dd></dl>
<dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#gaa5eb0e76dbc89596e1ce47ddb9edc4a0" title="Set the interrupt priority mask using CPU&#39;s PMR register.">GIC_SetInterfacePriorityMask</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gabc88483ecf94a2c222b644ecfa60eb9f">&#9670;&#160;</a></span>GIC_GetIRQStatus()</h2>

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          <td class="memname">__STATIC_INLINE uint32_t GIC_GetIRQStatus </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Get the status for a given interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to get status for. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd>0 - not pending/active, 1 - pending, 2 - active, 3 - pending and active</dd></dl>
<p>The return value is a combination of GIC's <a class="el" href="structGICDistributor__Type.html#a5eb8e1ef5a88293e2759c41f6057ccc4">ISACTIVER</a> and <a class="el" href="structGICDistributor__Type.html#a1c15cd75ce30d8946792e2a1a19556a5">ISPENDR</a> registers.</p>
<p>Bit 0 denotes interrupts pending bit (interrupt should be handled) and bit 1 denotes interrupts active bit (interrupt is currently handled). </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga397048004654f792649742f95bf8ae67">&#9670;&#160;</a></span>GIC_GetPriority()</h2>

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          <td class="memname">__STATIC_INLINE uint32_t GIC_GetPriority </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Read the current interrupt priority from GIC's IPRIORITYR register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be queried.</td></tr>
  </table>
  </dd>
</dl>
<p>Can be used to retrieve the actual priority depending on the GIC implementation. </p><dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71" title="Set the priority for the given interrupt in the GIC&#39;s IPRIORITYR register.">GIC_SetPriority</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#gafccf881f9517592f30489bcabcb738a8">&#9670;&#160;</a></span>GIC_GetTarget()</h2>

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          <td class="memname">__STATIC_INLINE uint32_t GIC_GetTarget </td>
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          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
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<p>Read the GIC's ITARGETSR register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt to acquire the configuration for. </td></tr>
  </table>
  </dd>
</dl>
<dl class="section return"><dt>Returns</dt><dd><a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c" title="Offset: 0x800 (R/W) Interrupt Targets Registers.">GICDistributor_Type::ITARGETSR</a></dd></dl>
<p>Read the current interrupt to CPU assignment for the given interrupt. </p><dl class="section see"><dt>See also</dt><dd><a class="el" href="group__GIC__functions.html#gae86bba705d0d4ef812b84d29d7b3ca2b" title="Sets the GIC&#39;s ITARGETSR register for the given interrupt.">GIC_SetTarget</a> </dd></dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga2de8850780af26e802ee4cc43e9da6e9">&#9670;&#160;</a></span>GIC_SendSGI()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_SendSGI </td>
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          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em>, </td>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>target_list</em>, </td>
        </tr>
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          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>filter_list</em>&#160;</td>
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          <td></td>
          <td>)</td>
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<p>Generate a software interrupt using GIC's SGIR register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Software interrupt to be generated. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">target_list</td><td>List of CPUs the software interrupt should be forwarded to. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">filter_list</td><td>Filter to be applied to determine interrupt receivers. </td></tr>
  </table>
  </dd>
</dl>

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<h2 class="memtitle"><span class="permalink"><a href="#ga5dfedeb5403656a77e0fef4e1cc2c0c6">&#9670;&#160;</a></span>GIC_SetBinaryPoint()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_SetBinaryPoint </td>
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          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>binary_point</em></td><td>)</td>
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<p>Configures the group priority and subpriority split point using CPU's BPR register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">binary_point</td><td>Amount of bits used as subpriority.</td></tr>
  </table>
  </dd>
</dl>
<p>The binary point defines the amount of priority bits used as a group priority and subpriorities.</p>
<p>Interrupts sharing the same group priority do not preempt each other. But interrupts having a higher group priority (lower value) preempt interrups with a lower group priority.</p>
<p>The subpriority defines the execution sequence of interrupts with the same group priority if multiple are pending at time. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#gaa5eb0e76dbc89596e1ce47ddb9edc4a0">&#9670;&#160;</a></span>GIC_SetInterfacePriorityMask()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_SetInterfacePriorityMask </td>
          <td>(</td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>priority</em></td><td>)</td>
          <td></td>
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<p>Set the interrupt priority mask using CPU's PMR register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>Priority mask to be set.</td></tr>
  </table>
  </dd>
</dl>
<p>Only interrupts with a higher priority (lower values) than the value provided are signaled. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga18fbddf7f3594df141c97f61a71da47c">&#9670;&#160;</a></span>GIC_SetPendingIRQ()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_SetPendingIRQ </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em></td><td>)</td>
          <td></td>
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<p>Sets the given interrupt as pending using GIC's ISPENDR register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be enabled.</td></tr>
  </table>
  </dd>
</dl>
<p>Adds the pending state to the corresponding interrupt. </p>

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<h2 class="memtitle"><span class="permalink"><a href="#ga27b9862b58290276851ec669cabf0f71">&#9670;&#160;</a></span>GIC_SetPriority()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_SetPriority </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>priority</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
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<p>Set the priority for the given interrupt in the GIC's IPRIORITYR register. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>The interrupt to be configured. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">priority</td><td>The priority for the interrupt, lower values denote higher priorities.</td></tr>
  </table>
  </dd>
</dl>
<p>Configures the priority of the given interrupt.</p>
<p>The available interrupt priorities are IMPLEMENTATION DEFINED. In order to query the actual priorities one can</p>
<div class="fragment"><div class="line"><a class="code hl_function" href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a>(IRQn_TIM1, UINT32_MAX);       <span class="comment">// try to configure lowest possible priority</span></div>
<div class="line">uint32_t actual = <a class="code hl_function" href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a>(IRQn_TIM1); <span class="comment">// retrieve actual lowest priority usable</span></div>
<div class="ttc" id="agroup__GIC__functions_html_ga27b9862b58290276851ec669cabf0f71"><div class="ttname"><a href="group__GIC__functions.html#ga27b9862b58290276851ec669cabf0f71">GIC_SetPriority</a></div><div class="ttdeci">__STATIC_INLINE void GIC_SetPriority(IRQn_Type IRQn, uint32_t priority)</div><div class="ttdoc">Set the priority for the given interrupt in the GIC's IPRIORITYR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1655</div></div>
<div class="ttc" id="agroup__GIC__functions_html_ga397048004654f792649742f95bf8ae67"><div class="ttname"><a href="group__GIC__functions.html#ga397048004654f792649742f95bf8ae67">GIC_GetPriority</a></div><div class="ttdeci">__STATIC_INLINE uint32_t GIC_GetPriority(IRQn_Type IRQn)</div><div class="ttdoc">Read the current interrupt priority from GIC's IPRIORITYR register.</div><div class="ttdef"><b>Definition:</b> core_ca.h:1664</div></div>
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<h2 class="memtitle"><span class="permalink"><a href="#gae86bba705d0d4ef812b84d29d7b3ca2b">&#9670;&#160;</a></span>GIC_SetTarget()</h2>

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          <td class="memname">__STATIC_INLINE void GIC_SetTarget </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="group__irq__ctrl__gr.html#ga7e1129cd8a196f4284d41db3e82ad5c8">IRQn_Type</a>&#160;</td>
          <td class="paramname"><em>IRQn</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype">uint32_t&#160;</td>
          <td class="paramname"><em>cpu_target</em>&#160;</td>
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        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
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<p>Sets the GIC's ITARGETSR register for the given interrupt. </p>
<dl class="params"><dt>Parameters</dt><dd>
  <table class="params">
    <tr><td class="paramdir">[in]</td><td class="paramname">IRQn</td><td>Interrupt to be configured. </td></tr>
    <tr><td class="paramdir">[in]</td><td class="paramname">cpu_target</td><td>CPU interfaces to assign this interrupt to.</td></tr>
  </table>
  </dd>
</dl>
<p>The <a class="el" href="structGICDistributor__Type.html#a6f1b07d48d3a9199f2effec8492f721c">ITARGETSR</a> registers provide an 8-bit CPU targets field for each interrupt supported by the GIC. This field stores the list of target processors for the interrupt. That is, it holds the list of CPU interfaces to which the Distributor forwards the interrupt if it is asserted and has sufficient priority. </p>

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